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CACHE

A set of read-only caches.
  FPGA proven NO
  ASIC proven NO

Introduction

If you work with computers you know what a cache is. You might have a vague idea how they work but implementing one requires a in-depth knowledge of their operation. In here you find a series of read-only caches. They have parameters for the depth of the cache, the width of the data and the width of the address. The line cache has a parameter for the size (length) of the line. The fast-flush cache has a parameter for the valid bits width. I also wrote a document how they work. For each cache you also need to download the appropriate memory model from the memories web page. All caches have been tested and can be synthesized. As usual they are provided with their (self-checking) test benches.
In the archive you find the following memories:

• async_ro_cache.v   Cache using a-synchronous memories
• ro_cache.v               One-way cache using single ported synchronous memories
• ro_cache2.v             Two-way cache using dual single ported synchronous memories
• ro_linecache.v         One-way cache using line reads
• ro_ff_cache.v           One-way cache with fast flush capabilities

The code can be found here. A document describing the caches is available here.
(Altough all the Verilog code is for free the cache document has copyright on it!)