A set of standard memories.
FPGA proven NO
ASIC proven NO
Memories are used on chip but also often in test-benches.
The memories archive contains a set of various memory models. All
models are synchronous memories. A-synchronous memories are rarely found
these days. All memories have parameters to control the width and depth.
At the moment the memories only support a depth which is a power of two.
Most models will map on Xilinx embedded memory macros. As usual the code
comes with some basic test-benches which I used to verify the memories.
In the archive you find the following memories:
The code can be found here.
A document describing the memories is available here.
As usual the code comes complete with the test benches I used to verify the operation. In this case the test-benches are NOT self-checking.