//
// Simple D-register behavioural model
// To be used in Xtal_startup testbench
// Has small delay to show a-sync behaviour
//

module Dreg(
  input      clk,
  input      reset_n,
  input      I,
  output reg Q
  );
begin
   always @(posedge clk or negedge reset_n)
      if (!reset_n)
         Q <= #1 1'b0;
      else
         Q <= #1 I;
end
endmodule // Dreg