//
// Third version Crystal oscillator stabilise start-up delay.
// Designed to work with start-up clock which may be 'bad'
// for a number of cycles at the begin.
// This version uses a positive edge triggered register.
// It also uses a active low reset.
// Because of this the circuit needs an inverter between the
// divide-by-two stages.
// This will increases the a-synchronous behaviour.
//
// Parameter STAGES specifies the number of div-2 stages
// Default = 10 thus about* 2^10 = 1024 clocks delay
// 
// *About because there may be 'bad' clock cycles 
// when the crystal starts oscillating
//
// This circuit assumes the ckl->Q delay plus an inverter 
// through the divider chain is less then half an crystal period.
// Also see the manual.
//

// 
// Design by G.J. van Loo, FenLogic Ltd, 20-January-2017.
//
// This program is free software. It comes without any guarantees or
// warranty to the extent permitted by applicable law. Although the
// author has attempted to find and correct any bugs in this free software
// program, the author is not responsible for any damage or losses of any
// kind caused by the use or misuse of the program. You can redistribute
// the program and or modify it in any form without obligations, but the
// author would appreciated if the credits stays in.
// 

module xtal_startup3 
#(parameter STAGES = 10)
   (
   input    xtal_raw,     // signal from crystal oscillator pad
   input    reset_n_raw,  // signal direct from reset-pad
   output   xtal_ok       // Clock from crystal which is assumed
                          // to have stabilised 
   );

wire [0:STAGES] clkdiv;
wire clk_done = clkdiv[STAGES];       // Last stage gone low

   assign clkdiv[0] = (xtal_raw & ~clk_done); // stop counting when done
   assign xtal_ok   = xtal_raw  &  clk_done;  // Start clock out when done 

genvar i;

generate
   for (i=0; i<STAGES; i=i+1)
   begin : xtalstart
      // Bog standard D-FF 
      // This one works of the negative edge of the clock
      // And is reset. Because of this it needs an extra inverter
      // per divde-by-two stage.
//`ifdef RTLSIM   
      // Behavioural and simulation model
      Dreg  Dff (
              .clk      (~clkdiv[i]), // Inverter in chain! 
              .reset_n  (reset_n_raw),
              .I        (~clkdiv[i+1]),
              .Q        (clkdiv[i+1]) 
             );
//`else
      // Instance your own library cell here  
      // BEWARE TO CHECK compatibility with the one above!!!! 
      // e.g. Formality
//`endif                 
   end // generate for
endgenerate

endmodule // xtal_startup3