//
// System reset generator
// Makes sure the rising edge of the reset is far
// away from any clock edges thus eliminating the 
// need to balance teh reset tree.
//

// 
// Design by G.J. van Loo, FenLogic Ltd, 27-January-2017.
//
// This program is free software. It comes without any guarantees or
// warranty to the extent permitted by applicable law. Although the
// author has attempted to find and correct any bugs in this free software
// program, the author is not responsible for any damage or losses of any
// kind caused by the use or misuse of the program. You can redistribute
// the program and or modify it in any form without obligations, but the
// author would appreciated if the credits stays in.
// 

module system_reset 
   (
   input       xtal_ok,     // signal from crystal oscillator pad
   input       reset_n_raw, // signal direct from reset-pad
   output      sys_clk,     // System clock 
   output reg  sys_reset_n  // reset to be distributed
   );

reg [7:0] count;         // Probably too big but who cares
reg       sys_reset_release;
reg       sys_clk_disable;

         
   // Can use xtal_ok and resert_raw here as we have no
   // not-reset-follow-up-registers in this little part of the code
   always @(negedge xtal_ok or negedge reset_n_raw)
   begin
      if (!reset_n_raw)
      begin
         count <= 8'h00;
         sys_clk_disable <= 1'b0;
         sys_reset_n <= 1'b0;
      end
      else
      begin
         // Tune these moments to your satisfaction.
         if (count!=8'hFF)
            count <= count+1;
         if (count==8'h20)
            sys_clk_disable <= 1'b1;
         if (count==8'h40)
            sys_reset_n <= 1'b1;
         if (count==8'h60)
            sys_clk_disable <= 1'b0;
      end
   end
   
   // Switch system clock off
   assign sys_clk  = xtal_ok & ~sys_clk_disable;
      
endmodule // system_reset